Controllable delay circuits can enjoy wide application in timing circuits. One very particular application can be to arrange delay cells into a ring to form a ring oscillator. Such a ring oscillator can be used, as but one example, as a voltage controlled oscillator (VCO) in a phase locked loop (PLL) circuit, or the like.
To better understand various aspects of the embodiments, a number of conventional circuits will now be described.
FIG. 8 shows a ring oscillator 800 formed by a number of delay cells 802-0 to 802-n arranged into a ring to generate an oscillating signal OSC. Each delay cell (802-0 to 802-n) can be essentially identical. A delay introduced by each delay cell (802-0 to 802-n) can be controlled according to a control voltage Vctrl. As but one example, as Vctrl increases, the oscillating frequency for circuit 800 can increase. A ring oscillator 800 used for voltage controlled oscillation can be employed in a phase locked loop (PLL). A PLL includes a control loop circuit that manipulates a VCO control voltage (Vctrl) in order to match an output signal phase to an input reference signal phase.
One type of conventional PLL is shown in FIG. 9 and designated by the general reference character 900. A conventional PLL 900 can include a phase and/or frequency (PFD) detector 902 that can determine the phase and/or frequency difference between an input signal φIN and an output signal φOUT. Each such signal can be frequency divided before such a comparison. In the example of FIG. 9, input signal φIN can be frequency divided by a divider 904, while output signal φOUT can be frequency divided by a divider 906. PFD 902 can output a phase (or frequency) difference value Δφ to a charge pump 908, which can charge a node 910 in response, to thereby generate a control voltage Vctrl. Such a control voltage (Vctrl) can be filtered by a loop filter 912. According to control voltage (Vctrl), a VCO 914 can generate output signal φOUT. Feedback path 916 can provide output signal φOUT back to PFD 902.
Referring still to FIG. 9, due to any number of circuit failures in the PLL feedback path 916, a PLL 900 can sometimes inadvertently fall into an unrecoverable state where the PLL 900 can no longer achieve phase lock. One such state can be a “runaway” condition, in which the PLL feedback path fails above a particular operating frequency, removing the PLL feedback from the PFD 902. Such a missing feedback signal will be detected as having a phase (and/or frequency) below that of the input signal φOUT, causing PFD 902 to show a positive phase difference. This can result in an increase in control voltage (Vctrl) and with it, an increase in PLL output phase and frequency.
Thus, because a PLL feedback path 916 is inoperative above a certain frequency, and the failure causes the PLL output frequency to increase, a PLL 900 can ultimately drive a control voltage (Vctrl) to a maximum (and with it the VCO maximum frequency) with the PLL 902 having no ability to correct the state and return to normal operation.
In order to correct a runaway condition, conventional approaches have attempted to detect when a maximum VCO frequency is reached according to an applied control voltage (Vctrl). Two conventional maximum frequency-detect circuits are shown in FIGS. 10 and 11. FIG. 10 shows a conventional arrangement in which a control voltage (Vctrl), utilized to establish the VCO frequency, can be compared with a reference voltage (Vref) by a comparator having hysteresis. In this way, a limit signal LIMIT can be activated when control voltage Vctrl exceeds a voltage Vref (or a Vref plus some predetermined amount). Conversely, an active limit signal LIMIT can be de-activated when control voltage Vctrl falls below voltage Vref (or is less than Vref by a predetermined amount). FIG. 11 shows a conventional arrangement utilizing a simple CMOS inverter to activate/de-activate a LIMIT signal based on a control voltage level. Thus, a limit is established according to the inverter threshold voltage.
In both conventional arrangements of FIGS. 10 and 11, a LIMIT signal can be utilized to signal a circuit or state machine to correct the runaway condition by forcing the reduction of a control voltage (Vctrl) such that a VCO frequency returns to below the runaway condition frequency threshold.
To better understand aspects of the embodiments, a conventional delay cell will be described. A conventional delay cell is shown in FIG. 12, and designated by the general reference character 1200. FIG. 12 shows one example of a current steering type delay cell that includes a first current source 1202, a second current source 1204, a differential pair of transistors 1206, a cross-coupled pair of transistors 1208, a first load 1210, and a second load 1212. A delay introduced by a delay cell 1200 can vary according to a current I1 provided to differential pair 1206 and a current I2 provided to cross coupled pair 1208. In addition, conventional delay cell 1200 can include control section 1214.
A control section 1214 can control current values I1 and I2 according to a control voltage (Vctrl) and reference voltage (Vref), and thus control a delay of delay cell 1200. In particular, a control section 1214 can draw a control current (ICTRL) according to a control voltage (Vctrl) and a reference current (IREF) according to a reference voltage (Vref). As a control voltage (Vctrl) increases, a control current (ICTRL) can be shunted through transistor M121 and R121, thus decreasing the magnitude of current I2, and thus decreasing a delay of delay cell 1200. Conversely, as a control voltage (Vctrl) decreases, less control current (ICTRL) can be shunted through transistor M121 and R121, thus increasing a magnitude of current I2. This can increase a delay of delay cell 1200.
Further, due to current source I120, as a control current (ICTRL) increases, a reference current (IREF) can decrease. Looked at in another way, current I2 is the difference between current I (1204) and IREF Likewise, current I1 is the difference between current 2I (1202) and ICTRL. In this way, the sum of currents I1 and I2 is constant.
Another conventional delay cell is described in detail in U.S. Pat. No. 6,911,857 B1, issued to Jonathon C. Stiff, on Jun. 28, 2005, titled CURRENT CONTROLLED DELAY CIRCUIT.
A drawback to conventional approaches to detecting a maximum VCO frequency, like those described above in FIGS. 10 and 11, is that such approaches can be too inaccurate for some delay cells and/or some applications. In particular, for some delay cells, a control voltage may not be representative of a full range of delay. Even more particularly, in a delay cell like that shown in FIG. 12, a steered current (I2) may reach a maximum value before a control voltage (Vctrl) reaches a maximum value. Thus, a maximum frequency (and hence the possibility of runaway) can be reached prior to a maximum control voltage level.
One representation of such an arrangement is shown in FIG. 13. FIG. 13 is a graph showing a steered current (12) (or a reference current (IREF)) versus an applied control voltage (Vctrl). A current level IRUN can correspond to a steered (or reference) current value at which VCO runaway can take place. A control voltage value VMAX can be a maximum control voltage level. As shown, a runaway condition can be reached prior to a maximum control voltage level.
It is understood that the graph of FIG. 13 is provided for illustrative purposes. An actual circuit response can vary (i.e., be non-linear).
In other cases, variations in manufacturing process, operating temperature and/or operating voltage may cause variations in delay cell response that are not adequately reflected by a comparator circuit and/or inverter, like those of FIGS. 10 and 11.